The present invention relates, in general, to semiconductor devices and, more particularly, to a method of forming a gate of a semiconductor device, which prevents a bowing profile from occurring during a gate etch process.
A NAND flash memory device has non-volatile memory properties including programming and erase characteristics, and a structure that is advantageous for high integration. The flash memory device has a structure in which a floating gate and a control gate are formed over a semiconductor substrate with a dielectric layer disposed therebetween. A gate insulating layer is formed below the floating gate.
The NAND flash memory device is formed by laminating the gate insulating layer, the floating gate, the dielectric layer, the control gate, etc., over the semiconductor substrate and then patterning by a gate etch process. This process is performed using etch conditions suitable for material for forming the respective layers in an in-situ manner. However, layers other than etch targets are patterned and sidewalls of the layers are exposed. Accordingly, problems arise because the layers other than the etch targets are unnecessarily etched and bowing occurs on sidewalls of a gate pattern.